FormalSIM
FORMAL VERIFICATION MADE SIMPLE
FormalSIM
FORMAL VERIFICATION MADE SIMPLE
Our MISSion
Solving the validation problem
While the number of chip designs continues to grow rapidly, validation continues to be the long pole in most chip design cycle. This is mainly being addressed by more use simulation and emulation. Formal Verification is also seeing increasing uptake in chip design compared to even just a few years ago. Contrary to the popular perception that Formal tools have matured, we believe that current Formal tools are far from ideal and there is plenty of room for the tools to improve. Our goal is to provide Formal Property Verifiers that can scale to full IP or even full CPU core level and thus provide a powerful option to tackle the hardware validation challenges.
What we offer
We offer Formal Property Verification tools that are highly scalable, produce easy to understand results that can be integrated with other validation results. Our FPV tools are also very easy to use which means they can be deployed early and deployed widely to shift left hardware design cycles. We believe our tools have the potential to shrink the time between RTL coded and RTL done to a matter of weeks instead of several quarters currently.